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HY64UD16162M Series
Document Title
1M x 16 bit Low Low Power 1T/1C Pseudo SRAM
Revision history
Revision No. History
1.0 1.1 Initial Revised - Change Pin Connection - Improve tOE from 45ns to 30ns - Correct State Diagram 1.2 Revised - Correct Package Dimension - Change Absolute Maximum Ratings 1.3 Revised - DC Electrical Characteristics ( IDPD,ICC1) - State Diagram - Power Up Sequence - Deep Power Down Sequence - Read/Write Cycle Note 1.4 1.5 Revised - DC Electrical Characteristics ( ICC1: 3mA - > 5mA) Revised - Improve Standby Current ISB1 from 100uA to 80uA - Add 70ns Part - Power Up Sequence 1.6 Revised - Improve ISB1@70ns 100uA to 85uA - Improve ISB1@85ns 80uA to 75uA - Improve ICC2@70ns 30mA to 25mA - Improve ICC2@85ns 30mA to 20mA - Improve Ambient Temperature C/E to E/I (0C~85C/-25C~85C -25C~85C/-40C~85C) - Improve Maximum Absolute Ratings (Vdd : -0.3V to 3.3V -0.3V to 3.6V) - Improve tOE@85ns 30ns to 20ns 1.7 Revised - Pin Description - Power Up & Deep Power Down Exit Sequence Mar. 11. ` 02 Final Feb. 27. ` 02 Preliminary Dec. 20. ` 01 Preliminary Nov. 14. ' 01 Preliminary Oct. 07. ` 01 Preliminary Jul.18. ' 01 Preliminary
Draft Date
Jan. 04. ' 01 Jul. 03. ' 01
Remark
Preliminary Preliminary
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Revision 1.7 March. 2002 1
HY64UD16162M Series
1M x 16 bit Low Low Power 1T/1C SRAM
DESCRIPTION
The HY64UD16162M is a 16Mbit 1T/1C SRAM featured by high-speed operation and super low power consumption. The HY64UD16162M adopts one transistor memory cell and is organized as 1,048,576 words by 16bits. The HY64UD16162M operates in the extended range of temperature and supports a wide operating voltage range. The HY64UD16162M also supports the deep power down mode for a super low standby current. The HY64UD16162M delivers the high-density low power SRAM capability to the high-speed low power system.
FEATURES
* CMOS Process Technology * 1M x 16 bit Organization * TTL compatible and Tri-state outputs * Deep Power Down : Memory cell data hold invalid * Standard pin configuration : 48-FBGA * Data mask function by /LB, /UB
PRODUCT FAMILY
Product No.
HY64UD16162M-DF70E HY64UD16162M-DF70I HY64UD16162M-DF85E HY64UD16162M-DF85I
Voltage [V]
2.7~3.3 2.7~3.3 2.7~3.3 2.7~3.3 1CS 1CS 1CS 1CS
Mode
with with with with /UB,/LB:tCS1 /UB,/LB:tCS1 /UB,/LB:tCS1 /UB,/LB:tCS1
Power Dissipation
(ISB1,Max) (IDPD,Max) (ICC2,Max) 85A 2A 25mA 85A 2A 25mA 75A 2A 20mA 75A 2A 20mA
Speed tRC[ns]
70 70 85 85
Temp. [C]
-25~85 -40~85 -25~85 -40~85
Note 1. tCS - /UB,/LB=High : Chip Deselect.
PIN CONNECTION (Top View)
/LB IO9 /OE /UB A0 A3 A5 A17 A1 A4 A6 A7 A16 A15 A13 A10 A2 /CS1 IO2 IO4 IO5 IO6 /WE A11 CS2 A0 IO1
BLOCK DIAGRAM
ROW DECODER
IO1
SENSE AMP
COLUMN DECODER
PRE DECODER
ADD INPUT BUFFER
IO10 IO11 Vss Vdd IO12
IO3 Vdd Vss A19 IO7 IO8 NC /CS1 CS2 /WE /OE /LB /UB
IO8 IO9
DATA I/O BUFFER
WRITE DRIVER
MEMORY ARRAY 1,024K x 16 BLOCK DECODER
IO13 DNU A14 A12 A9
IO15 IO14 IO16 A18 A19 A8
IO16
CONTROL LOGIC
PIN DESCRIPTION
Pin Name /CS1 CS2 /WE /LB /UB DNU NC Pin Function Chip Select Deep Power Down Write Enable Lower Byte(IO1~IO8) Upper Byte(IO9~IO16) Do Not Use No Connection Pin Name /OE IO1~IO8 IO9~IO16 A0~A19 Vdd Vss Pin Function Output Enable Lower Data Inputs/Outputs Upper Data Inputs/Outputs Address Inputs Power(2.7V~3.3V) Ground
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Revision 1.7 March. 2002 2
HY64UD16162M Series
ORDERING INFORMATION
Part Number Speed HY64UD16162M-E 70 / 85 HY64UD16162M-I 70 / 85 Note 1. E : Extended Temp. (-25C ~ 85C) 2. I : Industrial Temp. (-40C ~ 85C) Power LL-Part LL-Part Temperature E1 I2 Package FBGA FBGA
ABSOLUTE MAXIMUM RATINGS 1
Symbol VIN,VOUT Vdd TA TSTG PD TSOLDER Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. Parameter Input/Output Voltage Power Supply Ambient Temperature Storage Temperature Power Dissipation Ball Soldering Temperature & Time Rating
-0.3 to Vdd+0.3
-0.3 to 3.6 -25 to 85 -40 to 85 -55 to 150 1.0 260*10
Unit V V C C C W C*sec
Remark
HY64UD16162M-E HY64UD16162M-I
TRUTH TABLE
/CS1 CS2 H X X L L L L L L L L L H L H H H H H H H H H H /WE X X X L H H L H H L H H /OE X X X X L H X L H X L H /LB X X H L L L H H H L L L /UB X X H H H H L L L L L L Mode Deselected Deselected Deselected Write Read Output Disabled Write Read Output Disabled Write Read Output Disabled I/O Pin Power I/O1~I/O8 I/O9~I/O16 High-Z High-Z Standby High-Z High-Z Deep Power Down High-Z High-Z Standby DIN High-Z Active DOUT High-Z Active High-Z High-Z Active High-Z DIN Active High-Z DOUT Active High-Z High-Z Active DIN DIN Active DOUT DOUT Active High-Z High-Z Active
Note 1. H=VIH, L=VIL, X=don' t care(VIL or VIH) 2. /UB, /LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When /LB is LOW, data is written or read to the lower byte, I/O1 - I/O8. When /UB is LOW, data is written or read to the upper byte, I/O9 - I/O16.
Revision 1.7 March. 2002
3
HY64UD16162M Series
RECOMMENDED DC OPERATING CONDITION
Symbol Vdd VSS VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.7 0 2.2 -0.31 Typ. 3.0 Max. 3.3 0 Vdd+0.3 0.6 Unit V V V V
Note 1. VIL=-1.5V for pulse width less than 10ns Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
Vdd=2.7V~3.3V, TA= -25C to 85C(E) / -40C to 85C(I) Sym. Parameter Test Condition ILI Input Leakage Current VSSVINVdd ILO Output Leakage Current
VSSVOUTVdd, /CS1=VIH, CS2=VIH, /OE=VIH or /WE=VIL /CS1=VIL, CS2=VIH, VIN=VIH or VIL, II/O=0mA /CS1 0.2V, CS2 Vdd-0.2V, VIN 0.2V or VINVdd-0.2V, Cycle Time=1s. 100% Duty, II/O=0mA
/CS1=VIL, CS2=VIH, VIN=VIH or VIL, Cycle Time=Min. 100% Duty, II/O=0mA
Min. Typ. Max. Unit -1 1 A -1 1 A
ICC
Operating Power Supply Current
-
-
3
mA
ICC1 Average Operating Current ICC2 ISB ISB1 IDPD VOL VOH TTL Standby Current Standby Current(CMOS Input) Deep Power Down Curent Output Low Voltage Output High Voltage
-
-
5
mA
70ns
2.4
-
25 20 0.5 85 75 2 0.4 -
mA mA mA A A A V V
85ns /CS1,CS2=VIH or /UB,/LB= VIH /CS1, CS2Vdd-0.2V 70ns or /UB,/LB Vdd-0.2V 85ns CS2VSS+0.2V IOL=2.1mA IOH=-1.0mA
CAPACITANCE
(Temp = 25C, f=1.0MHz) Symbol Parameter CIN Input Capacitance(Add, /CS1, CS2, /WE, /OE, /UB, /LB) COUT Output Capacitance(I/O) Note : These parameters are sampled and not 100% tested Condition VIN=0V VI/O=0V Max. Unit 8 pF 10 pF
Revision 1.7 March. 2002
4
HY64UD16162M Series
AC CHARACTERISTICS
Vdd=2.7V~3.3V, TA = -25C to 85C(E) / -40C to 85C(I), unless otherwise specified -70 -85 # Symbol Parameter Min. Max. Min. Max. Read Cycle 1 tRC Read Cycle Time 70 85 2 tAA Address Access Time 70 85 3 tACS Chip Select Access Time 70 85 4 tOE Output Enable to Output Valid 20 20 5 tBA /LB, /UB Access Time 70 85 6 tCLZ Chip Select to Output in Low Z 10 10 7 tOLZ Output Enable to Output in Low Z 5 5 8 tBLZ /LB, /UB Enable to Output in Low Z 10 10 9 tCHZ Chip Disable to Output in High Z 0 20 0 30 10 tOHZ Out Disable to Output in High Z 0 20 0 30 11 tBHZ /LB, /UB Disable to Output in High Z 0 20 0 30 12 tOH Output Hold from Address Change 10 10 Write Cycle 13 tWC Write Cycle Time 70 85 14 tCW Chip Selection to End of Write 60 70 15 tAW Address Valid to End of Write 60 70 16 tBW /LB, /UB Valid to End of Write 60 70 17 tAS Address Set-up Time 0 0 18 tWP Write Pulse Width 50 60 19 tWR Write Recovery Time 0 0 20 tWHZ Write to Output in High Z 0 20 0 30 21 tDW Data to Write Time Overlap 30 30 22 tDH Data Hold from Write Time 0 0 23 tOW Output Active from End of Write 5 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
AC TEST CONDITIONS
TA = -25C to 85C(E) / -40C to 85C(I), unless otherwise specified Parameter Value Input Pulse Level 0.4V to 2.2V Input Rising and Fall Time 5ns Input and Output Timing Reference Level 1.5V Output Load See Below
AC TEST LOADS
DOUT Z0=50 Ohm RL=50 Ohm VL=1.5 V CL1 =30 pF
Note 1. Including jig and scope capacitance.
Revision 1.7 March. 2002
5
HY64UD16162M Series
Power-Up Sequence
1. Supply power. 2. Maintain stable power for longer than 200s.
Deep Power Down Entry Sequence
1. Keep CS2 low state. Deep power down mode is maintained while CS2 is low state.
Deep Power Down Exit Sequence
1. Keep CS2 high state. 2. Maintain stable power for longer than 200s.
STATE DIAGRAM
Power On Power On
Power-Up Sequence
Deep Power Down Exit Sequence
CS2=VIH
Wait 200s Wait 200 200s
/ CS1=VIL, CS2=VIH, /UB&/LBVIH
Active Active
CS2=VIL CS2=VIH, /CS1=VIH or /UB,/LB=VIH
Standby Standby Mode Mode
CS2=VIL
Deep Power Deep Power Down Mode Down Mode
Deep Power Down Entry Sequence
STANDBY MODE CHARACTERISTICS
Mode Standby Deep Power Down Memory Cell Data Valid Invalid Standby Current[A] 85 / 70ns 75 / 85ns 2 Wait Time[s] 0 200
Revision 1.7 March. 2002
6
HY64UD16162M Series
TIMING DIAGRAM
READ CYCLE 1 ( Note 1, 4 )
tRC ADD tAA /CS1 tACS tCHZ(3) CS2 Vih tBA tBHZ(3) /OE tOLZ(3) tBLZ(3) tCLZ(3) Data Out High-Z Data Valid tOE tOHZ(3) tOH
/UB, /LB
READ CYCLE 2 ( Note 1, 2, 4 )( CS2=Vih )
tRC ADD tAA tOH Data Out Previous Data Data Valid tOH
READ CYCLE 3 ( Note 1, 2, 4 )( CS2=Vih )
/CS1 /UB, /LB tCLZ(3) Data Out High-Z Data Valid
tACS
tCHZ(3)
Notes : 1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and CS2 are in active status. 2. /OE = VIL 3. tCHZ, tBHZ and tOHZ are defined as the time at which the outputs achieve the high impedance state and tOLZ,tBLZ and tCLZ are defined as the time at which the outputs achieve the low impedance state. These are not referenced to output voltage levels. 4. /CS1 in high for the standby, low for active. /UB and /LB in high for the standby, low for active.
Revision 1.7 March. 2002
7
HY64UD16162M Series WRITE CYCLE 1 ( Note 1, 4, 5, 9, 10 ) ( /WE Controlled )
tWC ADD tWR(2) /CS1 tCW
CS2
Vih
tAW tBW
/UB, /LB
/WE High-Z
tAS
tWP tDW tDH
Data In
Data Valid tWHZ(3,8) tOW
(6) (7)
Data Out
WRITE CYCLE 2 ( Note 1, 4, 5, 9, 10 ) ( /CS1 Controlled )
tWC ADD tAS /CS1 tCW tWR(2)
CS2
Vih
tAW tBW
/UB, /LB
/WE High-Z
tWP tDW tDH
Data In
Data Valid
Data Out
High-Z
Notes : 1. A write occurs during the overlap of low /CS1, low /WE and low /UB and/or /LB. 2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS1, /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. /OE is continuously low (/OE=VIL) 6. Q(data out) is the invalid data. 7. Q(data out) is the read data of the next address. 8. tWHZ is defined as the time at which the outputs achieve the high impedance state. It is not referenced to output voltage levels. 9. /CS1 in high for the standby, low for active. /UB and /LB in high for the standby, low for active. 10. Do not input data to the I/O pins while they are in the output state. Revision 1.7 March. 2002
8
HY64UD16162M Series
AVOID TIMING
Hynix 1T/1C SRAM has a timing which is not supported at read operation. If your system has multiple invalid address signal shorter than tRC during over 10us at read operation which showed in abnormal timing, Hynix 1T/1C SRAM needs a normal read timing at least during 10us which showed in avoidable timing(1) or toggle the /CS1 to high(tRC) one time at least which showed in avoidable timing(2)
ABNORMAL TIMING
/CS1
/WE < tRC ADD
10us
AVOIDABLE TIMING(1)
/CS1
/WE
10us tRC
ADD
AVOIDABLE TIMING(2)
/CS1
tRC
/WE < tRC ADD
10us
Revision 1.7 March. 2002
9
HY64UD16162M Series
PACKAGE DIMENSION
48ball Fine Pitch Ball Grid Array Package(F)
TOP VIEW TOP VIEW BOTTOM VIEW BOTTOM VIEW
A1 CORNER INDEX AREA
B1 B A
A1 INDEX MARK
A A B C C D C1 E F G H 6 5 B/2 SIDE VIEW SIDE VIEW 5 C
E
C/2
4
3
2
1
E1 E2 SEATING PLANE A R 4
3 D(DIAMETER) unit : mm Symbol A B B1 C C1 D E E1 E2 R
Revision 1.7 March. 2002
NOTE. 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE MILLIMETERS. 3. DIMENSION "D" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE CROWN OF THE SOLDER BALLS. 5. THIS IS A CONTROLLING DIMENSION.
Min. 6.90 7.90 0.30 0.20 -
Typ. 0.75 7.00 3.75 8.00 5.25 0.35 1.00 0.75 0.25 -
Max. 7.10 8.10 0.40 1.10 0.30 0.08
10
HY64UD16162M Series MARKING INFORMATION
Package
Marking Example
H
Y
U
D
1
6
1
6
2
M
FBGA
c
s
s
t
y
y
w
w
p
x
x
x
x
x
K
O
R
Index
*
HYUD16162M HY U D 16 16 2 M c ss
: : : : : : : :
Part Name HYNIX Power Supply Tech. + Classification Bit Organization Density Mode Version
: : : : : :
3.0V(2.7V~3.3V) 1T+1C x16 16M 1CS with /UB,/LB;tCS 1st Generation
* *
: Power Consumption : Speed : Temperature
*t
: D - Low Low Power : 70 - 70ns 85 - 85ns : E - Extended(-25 ~ 85C) I - Industrial(-40 ~ 85C)
* yy * ww *p * xxxxx * KOR
: Year (ex : 01 = year 2001, 02= year 2002) : Work Week ( ex : 12 = work week 12 ) : Process Code : Lot No. : Origin Country
Note
- Capital Letter - Small Letter
: Fixed Item : Non-fixed Item
Revision 1.7 March. 2002
11

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